An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11mm2) by adopting 90nm\r\nSi CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates\r\nreference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates highfrequency\r\noutput signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise\r\ncharacteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was -88 dBc/Hz at a\r\nPLL output frequency of 7.2GHz (= 144 Ã?â?? 50MHz); with injection locking, the noise was -101 dBc/Hz (spur level: -31 dBc; power\r\nconsumption from a 1.0V power supply: 25mW).
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